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<div id="main_wrapper">
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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">PnR Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">PnR Summaries</a></li>-->
<li><a href="#PnR_Details" style=" font-size: 16px;">PnR Details</a>
<li><a href="#Resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#Resource_Usage_Summary" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#I/O_Bank_Usage_Summary" style=" font-size: 14px;">I/O Bank Usage Summary</a></li>
<li><a href="#Global_Clock_Usage_Summary" style=" font-size: 14px;">Global Clock Usage Summary</a></li>
<li><a href="#Global_Clock_Signals" style=" font-size: 14px;">Global Clock Signals</a></li>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
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<div id="content">
<h1><a name="Message">PnR Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>PnR Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun_pro\GW1NR_9C\impl\gwsynthesis\GY_riscv.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\GaoYun_pro\GW1NR_9C\CST\PIN.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Aug 08 11:04:31 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="PnR_Details">PnR Details</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<table class="summary_table">
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
   Placement Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
   Placement Phase 1: CPU time = 0h 0m 0.215s, Elapsed time = 0h 0m 0.214s
   Placement Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
   Placement Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
   Total Placement: CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s
Running routing:
   Routing Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.004s
   Routing Phase 1: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
   Routing Phase 2: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s
   Total Routing: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s
Generate output files:
   CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s, Peak memory usage = 261MB</td>
</tr>
</table>
<br/>
<h1><a name="Resource">Resource</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>4578/8640</td>
<td>52%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>4578(4187 LUT, 391 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --SSRAM(RAM16)</td>
<td>0</td>
<td>-</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1275/6693</td>
<td>19%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
<td>0/6480</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>1269/6480</td>
<td>19%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
<td>0/213</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as FF</td>
<td>6/213</td>
<td>2%</td>
</tr>
<tr>
<td class="label">CLS</td>
<td>2697/4320</td>
<td>62%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>43</td>
<td>-</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>31</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>6</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>25</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Inout Buf</td>
<td>0</td>
<td>-</td>
</tr>
<tr>
<td class="label">IOLOGIC</td>
<td>3 OSER10<br/></td>
<td>6%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>8 SP<br/>2 SDPB<br/></td>
<td>38%</td>
</tr>
<tr>
<td class="label">DSP</td>
<td>0</td><td>0%</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>1/2</td>
<td>50%</td>
</tr>
<tr>
<td class="label">DCS</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DQCE</td>
<td>0/24</td>
<td>0%</td>
</tr>
<tr>
<td class="label">OSC</td>
<td>0/1</td>
<td>0%</td>
</tr>
<tr>
<td class="label">User Flash</td>
<td>0/1</td>
<td>0%</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>1/8</td>
<td>12%</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DHCEN</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DHCENC</td>
<td>0/4</td>
<td>0%</td>
</tr>
</table>
<h2><a name="I/O_Bank_Usage_Summary">I/O Bank Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>I/O Bank</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">bank 1</td>
<td>9/25(36%)</td>
</tr>
<tr>
<td class="label">bank 2</td>
<td>13/23(56%)</td>
</tr>
<tr>
<td class="label">bank 3</td>
<td>15/23(65%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Usage_Summary">Global Clock Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Global Clock</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>2/8(25%)</td>
</tr>
<tr>
<td class="label">SECONDARY</td>
<td>2/8(25%)</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
<td>3/4(75%)</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>1/2(50%)</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>1/8(12%)</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8(0%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Signal</b></td>
<td><b>Global Clock</b></td>
<td><b>Location</b></td>
</tr>
<tr>
<td class="label">clk_p</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">spi_clk_inter</td>
<td>PRIMARY</td>
<td> TR TL BR</td>
</tr>
<tr>
<td class="label">n325_7</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">pll_lock</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">clk_d</td>
<td>HCLK</td>
<td>RIGHT[0]</td>
</tr>
<tr>
<td class="label">clk_p5</td>
<td>HCLK</td>
<td>TOP[0]</td>
</tr>
</table>
<br/>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">clk</td>
<td></td>
<td>52/1</td>
<td>Y</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">resetn</td>
<td></td>
<td>4/3</td>
<td>Y</td>
<td>in</td>
<td>IOL5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">uart_rx</td>
<td></td>
<td>18/2</td>
<td>Y</td>
<td>in</td>
<td>IOB2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">spi_miso</td>
<td></td>
<td>85/3</td>
<td>Y</td>
<td>in</td>
<td>IOT8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">dbg_uart_rx</td>
<td></td>
<td>31/2</td>
<td>Y</td>
<td>in</td>
<td>IOB15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">key[1]</td>
<td></td>
<td>3/3</td>
<td>Y</td>
<td>in</td>
<td>IOT2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">trap</td>
<td></td>
<td>11/3</td>
<td>Y</td>
<td>out</td>
<td>IOL16[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[0]</td>
<td></td>
<td>26/2</td>
<td>N</td>
<td>out</td>
<td>IOB8[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[1]</td>
<td></td>
<td>10/3</td>
<td>Y</td>
<td>out</td>
<td>IOL15[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[2]</td>
<td></td>
<td>13/3</td>
<td>Y</td>
<td>out</td>
<td>IOL21[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[3]</td>
<td></td>
<td>14/3</td>
<td>Y</td>
<td>out</td>
<td>IOL22[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[4]</td>
<td></td>
<td>15/3</td>
<td>Y</td>
<td>out</td>
<td>IOL25[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[5]</td>
<td></td>
<td>16/3</td>
<td>Y</td>
<td>out</td>
<td>IOL26[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[6]</td>
<td></td>
<td>29/2</td>
<td>N</td>
<td>out</td>
<td>IOB13[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte[7]</td>
<td></td>
<td>25/2</td>
<td>N</td>
<td>out</td>
<td>IOB8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">out_byte_en</td>
<td></td>
<td>80/3</td>
<td>N</td>
<td>out</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">clk_o</td>
<td></td>
<td>81/3</td>
<td>N</td>
<td>out</td>
<td>IOT11[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">mem_valid_o</td>
<td></td>
<td>82/3</td>
<td>N</td>
<td>out</td>
<td>IOT11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">mem_ready_o</td>
<td></td>
<td>27/2</td>
<td>N</td>
<td>out</td>
<td>IOB11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">led</td>
<td></td>
<td>83/3</td>
<td>N</td>
<td>out</td>
<td>IOT10[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">uart_tx</td>
<td></td>
<td>17/2</td>
<td>Y</td>
<td>out</td>
<td>IOB2[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">tmds_clk_p</td>
<td>tmds_clk_n</td>
<td>69,68/1</td>
<td>Y</td>
<td>out</td>
<td>IOT42</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">tmds_d_p[0]</td>
<td>tmds_d_n[0]</td>
<td>71,70/1</td>
<td>Y</td>
<td>out</td>
<td>IOT41</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">tmds_d_p[1]</td>
<td>tmds_d_n[1]</td>
<td>73,72/1</td>
<td>Y</td>
<td>out</td>
<td>IOT39</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">tmds_d_p[2]</td>
<td>tmds_d_n[2]</td>
<td>75,74/1</td>
<td>Y</td>
<td>out</td>
<td>IOT38</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">psram_clk</td>
<td></td>
<td>40/2</td>
<td>Y</td>
<td>out</td>
<td>IOB33[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">psram_cs</td>
<td></td>
<td>42/2</td>
<td>Y</td>
<td>out</td>
<td>IOB41[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">spi_clk</td>
<td></td>
<td>84/3</td>
<td>N</td>
<td>out</td>
<td>IOT10[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">spi_mosi</td>
<td></td>
<td>86/3</td>
<td>Y</td>
<td>out</td>
<td>IOT8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">uart2_tx</td>
<td></td>
<td>39/2</td>
<td>N</td>
<td>out</td>
<td>IOB33[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">dbg_uart_tx</td>
<td></td>
<td>32/2</td>
<td>Y</td>
<td>out</td>
<td>IOB15[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">psram_dio[0]</td>
<td></td>
<td>35/2</td>
<td>Y</td>
<td>io</td>
<td>IOB29[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">psram_dio[3]</td>
<td></td>
<td>41/2</td>
<td>Y</td>
<td>io</td>
<td>IOB41[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">3/3</td>
<td>key[1]</td>
<td>in</td>
<td>IOT2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">88/3</td>
<td>-</td>
<td>in</td>
<td>IOT5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">87/3</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">86/3</td>
<td>spi_mosi</td>
<td>out</td>
<td>IOT8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">85/3</td>
<td>spi_miso</td>
<td>in</td>
<td>IOT8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">84/3</td>
<td>spi_clk</td>
<td>out</td>
<td>IOT10[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">83/3</td>
<td>led</td>
<td>out</td>
<td>IOT10[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">82/3</td>
<td>mem_valid_o</td>
<td>out</td>
<td>IOT11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">81/3</td>
<td>clk_o</td>
<td>out</td>
<td>IOT11[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">80/3</td>
<td>out_byte_en</td>
<td>out</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">79/3</td>
<td>-</td>
<td>in</td>
<td>IOT12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">77/1</td>
<td>-</td>
<td>in</td>
<td>IOT37[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">76/1</td>
<td>-</td>
<td>in</td>
<td>IOT37[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">75/1</td>
<td>tmds_d_p[2]</td>
<td>out</td>
<td>IOT38[A]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">74/1</td>
<td>tmds_d_n[2]</td>
<td>out</td>
<td>IOT38[B]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">73/1</td>
<td>tmds_d_p[1]</td>
<td>out</td>
<td>IOT39[A]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">72/1</td>
<td>tmds_d_n[1]</td>
<td>out</td>
<td>IOT39[B]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">71/1</td>
<td>tmds_d_p[0]</td>
<td>out</td>
<td>IOT41[A]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">70/1</td>
<td>tmds_d_n[0]</td>
<td>out</td>
<td>IOT41[B]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">69/1</td>
<td>tmds_clk_p</td>
<td>out</td>
<td>IOT42[A]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">68/1</td>
<td>tmds_clk_n</td>
<td>out</td>
<td>IOT42[B]</td>
<td>LVCMOS33D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">17/2</td>
<td>uart_tx</td>
<td>out</td>
<td>IOB2[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">18/2</td>
<td>uart_rx</td>
<td>in</td>
<td>IOB2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">19/2</td>
<td>-</td>
<td>in</td>
<td>IOB4[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">20/2</td>
<td>-</td>
<td>in</td>
<td>IOB4[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">25/2</td>
<td>out_byte[7]</td>
<td>out</td>
<td>IOB8[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">26/2</td>
<td>out_byte[0]</td>
<td>out</td>
<td>IOB8[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">27/2</td>
<td>mem_ready_o</td>
<td>out</td>
<td>IOB11[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">28/2</td>
<td>-</td>
<td>in</td>
<td>IOB11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">29/2</td>
<td>out_byte[6]</td>
<td>out</td>
<td>IOB13[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">30/2</td>
<td>-</td>
<td>in</td>
<td>IOB13[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">31/2</td>
<td>dbg_uart_rx</td>
<td>in</td>
<td>IOB15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">32/2</td>
<td>dbg_uart_tx</td>
<td>out</td>
<td>IOB15[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">33/2</td>
<td>-</td>
<td>in</td>
<td>IOB23[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">34/2</td>
<td>-</td>
<td>in</td>
<td>IOB23[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">35/2</td>
<td>psram_dio[0]</td>
<td>io</td>
<td>IOB29[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">36/2</td>
<td>-</td>
<td>in</td>
<td>IOB29[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">37/2</td>
<td>-</td>
<td>in</td>
<td>IOB31[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">38/2</td>
<td>-</td>
<td>in</td>
<td>IOB31[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">39/2</td>
<td>uart2_tx</td>
<td>out</td>
<td>IOB33[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">40/2</td>
<td>psram_clk</td>
<td>out</td>
<td>IOB33[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">41/2</td>
<td>psram_dio[3]</td>
<td>io</td>
<td>IOB41[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">42/2</td>
<td>psram_cs</td>
<td>out</td>
<td>IOB41[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">47/2</td>
<td>-</td>
<td>in</td>
<td>IOB43[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">4/3</td>
<td>resetn</td>
<td>in</td>
<td>IOL5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">5/3</td>
<td>-</td>
<td>in</td>
<td>IOL11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">6/3</td>
<td>-</td>
<td>in</td>
<td>IOL11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">7/3</td>
<td>-</td>
<td>in</td>
<td>IOL12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">8/3</td>
<td>-</td>
<td>out</td>
<td>IOL13[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">9/3</td>
<td>-</td>
<td>in</td>
<td>IOL13[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">10/3</td>
<td>out_byte[1]</td>
<td>out</td>
<td>IOL15[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">11/3</td>
<td>trap</td>
<td>out</td>
<td>IOL16[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">13/3</td>
<td>out_byte[2]</td>
<td>out</td>
<td>IOL21[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">14/3</td>
<td>out_byte[3]</td>
<td>out</td>
<td>IOL22[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">15/3</td>
<td>out_byte[4]</td>
<td>out</td>
<td>IOL25[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">16/3</td>
<td>out_byte[5]</td>
<td>out</td>
<td>IOL26[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">63/1</td>
<td>-</td>
<td>in</td>
<td>IOR5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">62/1</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">61/1</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">60/1</td>
<td>-</td>
<td>in</td>
<td>IOR12[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">59/1</td>
<td>-</td>
<td>in</td>
<td>IOR12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">57/1</td>
<td>-</td>
<td>in</td>
<td>IOR13[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">56/1</td>
<td>-</td>
<td>in</td>
<td>IOR14[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">55/1</td>
<td>-</td>
<td>in</td>
<td>IOR14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">54/1</td>
<td>-</td>
<td>in</td>
<td>IOR15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">53/1</td>
<td>-</td>
<td>in</td>
<td>IOR15[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">52/1</td>
<td>clk</td>
<td>in</td>
<td>IOR17[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">51/1</td>
<td>-</td>
<td>in</td>
<td>IOR17[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">50/1</td>
<td>-</td>
<td>in</td>
<td>IOR22[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">49/1</td>
<td>-</td>
<td>in</td>
<td>IOR24[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">48/1</td>
<td>-</td>
<td>in</td>
<td>IOR24[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
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